Online Employability Enhancement Program VLSI ReVisited: From Analog to Digital

Online Employability Enhancement Program VLSI ReVisited: From Analog to Digital 2021

5 weeks intensive online Employability Enhancement Program technically co-sponsored by IEEE Circuits and Systems Society - Delhi Chapter

Program Dates: 7th June 2021 to 9th July 2021
Last Date of Registration: 1st June 2021
Early Bird discounts until 7th May 2021
Venue: Online

Course Objectives

  • Design low power high speed digital circuits and memory
  • Design operational amplifier using CMOS
  • Design a ADC using CMOS
  • Hardware and software optimization using Gem5 Simulator
  • Image Processing via Verilog and High Level Synthesis (HLS)

Course Highlights

  • 5 Weeks (June 7 to July 9)
  • 75 Online Teaching Hours
  • 75 Take-home Assignment Hours
  • Hands-on Sessions every week
  • Additional (complimentary) session for participants from industry and from colleges with SMDP tool set.
  • Experts over 5-40 years of experience
  • 1-Month free access to recorded lectures

Online Registration    Brochure

Registration Rates* - VLSI ReVisited 2021



Registration rates for full program (in INR)
Indian Students Indian Faculty/ International Students Partner Industry Participant Regular Industry Participant/ Other International Participants
Early Bird (before 7-May-2021) IEEE Member 3600 5400 10800 14400
Others^ 4500 6750 13500 18000
Regular IEEE Member 4000 6000 12000 16000
Others^ 5000 7500 15000 20000



Registration rates for week (in INR)
Indian Students Indian Faculty/ International Students Partner Industry Participant Regular Industry Participant/ Other International Participants
Early Bird (before 7-May-2021) IEEE Member 1440 2160 4320 5760
Others^^ 1800 2700 5400 7200
Regular IEEE Member 1600 2400 4800 6400
Others^^ 2000 3000 6000 8000

* GST @ 18% extra

^ Additional 10% discount on group registrations of more than 4 (Not valid for IEEE members)