Sneh Saurabh obtained his Ph.D. from IIT Delhi in 2012 and B.Tech. (EE) from IIT Kharagpur in the year 2000. He has rich experience in the semiconductor industry, having spent 16 years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation. He has been involved in developing some of the well-established industry-standard EDA tools for clock synchronization, constraints management, STA, formal verification, and physical design. He has been teaching semiconductor-specific courses since 2016 at IIIT Delhi. His teaching has been rated excellent by students consistently, and he has received the Teaching Excellence award for seven consecutive semesters at IIITD. His current research interests are in the areas of VLSI Design and Automation, Energy-Efficient Systems, and Stochastic Computational Frameworks. He is the author of the books “Introduction to VLSI Design Flow” and “Fundamentals of Tunnel Field-Effect Transistors” and holds three US patents. He is an Editor (IETE Technical Review), an Associate Editor (IEEE Access), a Review Editor (Frontiers in Electronics Integrated Circuits and VLSI), and a Senior Member of IEEE.