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VLSI Revisited 2022

VLSI Revisited 2022

Executive Summary

IIIT Delhi and IEEE CASS-CSS Delhi Chapter present 6- weeks Online Summer School on VLSI for Employability Enhancement for Faculty, recent graduates working in industry, and graduating students. Facilitated by stellar faculty with decades of teaching and industry work experience, this refresher program includes 180 fast-paced contact hours including theory and lab sessions. The program has been highly acclaimed in the previous runs as a perfect launchpad for a successful career in VLSI Circuits and System Design.



Schedule

WeekSubjectContentTools/ Languages Used in Labs
Week-1 (20-24 June)Digital VLSI and Memory Design (Dr. Anuj Grover)
  • » Introduction to VLSI Technology
  • » Logic Design Styles – PTL, Static and Dynamic
  • » Sequential Circuits
  • » Memory Cell and Periphery Circuits
  • » Electric/ Virtuoso
  • » LTSpice/ Eldo
Week-2 (27 June – 1 July)Analog IC Design (Prof. G.S. Visweswaran)
  • » Basics of MOS Transistors
  • » Basic Amplifier and Frequency Response
  • » Current Mirrors
  • » Differential Amplifiers
  • » Operational Amplifiers
  • » Electric/ Virtuoso
  • » LTSpice/ Spectre
Week-3 (4-8 July)Mixed Signal Design (Prof. S. S. Jamuar, Dr. Rakesh Palani)
  • » Characteristics and Testing of Data Converters
  • » Nyquist Rate Data Converters
  • » Design of S/H and Comparator Circuits
  • » Sigma Delta ADC and DAC
  • » Electric/ Virtuoso
  • » LTSpice/ Spectre
Week-4 (11-15 July)Computer Architecture & SoC (Dr. Sujay Deb)
  • » Introduction to Computer Architecture
  • » In-depth study of pipelining and hazards
  • » Superscalar architectures
  • » Processor Memory sub-system
  • » Multi-core SoCs and Research Directions
  • » Gem5
Week-5 (18-22 July)ASIC Design & Verification (Dr. Sneh Saurabh)
  • » Overview of ASIC Design Flow
  • » Logic Synthesis
  • » Static Timing Analysis
  • » Formal Verification
  • » Physical Design
  • » Yosys
  • » OpenSTA
  • » Openroad
Week-6 (25-29 July)Digital System Design (Dr. Sumit J. Darak)
  • » Finite State Machine
  • » AXI Protocol
  • » Image Processing (Image Filtering)
  • » High Level Synthesis (HLS)
  • » Image Processing via HLS
  • » C++ to Verilog via HLS

Registration Rates $*

Registration rates per module (in INR)
Indian StudentsIndian Faculty/ International StudentsPartner Industry ParticipantIndustry / International Participants
IEEE Member2000320064008000
Others^25004000800010000
50% Discounted Registration rates for full program (6-weeks) (in INR)
IEEE Member600096001920024000
Others^7500120002400030000
$ 10% Early Bird discount for first 100 registrations or until May 22 May 29, 2022 (whichever is earlier)
* rates are inclusive of GST
^ Additional 10% discount on group registrations of 4 or more

Last updated: 24-05-2022